1. Field of the Invention
This invention relates to an arbiter circuit providing priority control of dynamic memory operations as a memory access signal control circuit.
2. Description of the Prior Art
As the FIFO (First In First Out) memory device, for example, two commercial products are known under names, .mu.PD41101C and CXK1202S, respectively. Also some FIFO memory devices have been disclosed in the 1986 national conference of the Institute of Electronics and Communication Engineers of Japan. When disclosed, all these devices were designated as the line memory. Though characterized by fast read and write cycles, each as fast as around 30 nsec, these devices have modest storage capacities of about 2 kbits per port at most.
To increase the storage capacity, the memory configuration must be simplified as much as possible to allow for higher circuit integration. Being designed for a memory configuration similar to the static RAM (Random Access Memory), however, the above FIFO memory devices, though simple to control for read and write and capable of readily achieving highspeed operation, have a problem of insufficient circuit integration.
Meanwhile, a semiconductor memory device of the DRAM (Dynamic Random Access Memory) type provided with dynamic memory elements and having an additional internal circuit as a means to provide control for memory refreshing without recourse to any external control signal is described in application Ser. No. 083,555 filed Aug. 7, 1987. The basic design of this memory device includes line buffers for serial-parallel and parallel-serial conversion of data, further having an oscillator or oscillators, for example, of ring type, a counter or counters to count oscillation pulses from such oscillators, signal generators to generate the read and write request signals, another signal generator to generate the refresh request signal, and an arbiter circuit to determine priority depending on circumstances between read, write and refresh request signals as these signals are generated.